Texas Instruments /MSP432E411Y /LCD0 /LIDDCS0CFG

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Interpret as LIDDCS0CFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LCD_LIDDCS0CFG_GAP 0LCD_LIDDCS0CFG_RDHOLD 0LCD_LIDDCS0CFG_RDDUR 0LCD_LIDDCS0CFG_RDSU 0LCD_LIDDCS0CFG_WRHOLD 0LCD_LIDDCS0CFG_WRDUR 0LCD_LIDDCS0CFG_WRSU

Description

LCD LIDD CS0 Configuration

Fields

LCD_LIDDCS0CFG_GAP

Field value defines the number of LCDMCLK cycles (GAP +1) between the end of one CS0 (LCDAC) device access and the start of another CS0 (LCDAC) device access unless the two accesses are both reads

LCD_LIDDCS0CFG_RDHOLD

Read Strobe (RD) Hold cycles

LCD_LIDDCS0CFG_RDDUR

Read Strobe (RD) Duration cycles

LCD_LIDDCS0CFG_RDSU

Read Strobe (RD) Set-Up cycles

LCD_LIDDCS0CFG_WRHOLD

Write Strobe (WR) Hold cycles

LCD_LIDDCS0CFG_WRDUR

Write Strobe (WR) Duration Cycles

LCD_LIDDCS0CFG_WRSU

Write Strobe (WR) Set-Up Cycles

Links

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